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charge pump, 7-channel smart led driver with i 2 c interface ADP8860 rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. trademarks and registered trademarks are the property of their respective owners. 07967-001 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ?2009 analog devices, inc. all rights reserved. features charge pump with automatic gain selection of 1, 1.5, and 2 for maximum efficiency up to two built-in comparator inputs with programmable modes for ambient light sensing outdoor, office, and dark modes for maximum backlight power savings 7 independent and programmable led drivers 6 drivers capable of 30 ma (typical) 1 driver capable of 60 ma (typical) programmable maximum current limit (128 levels) standby mode for <1 a current consumption 16 programmable fade in and fade out times 0.1 sec to 5.5 sec choose from linear, square, or cubic rates fading override i 2 c-compatible interface for all programming dedicated reset pin and built-in power-on reset (por) short-circuit, overvoltage, and overtemperature protection internal soft start to limit inrush currents input-to-output isolation during faults or shutdown operation down to v in = 2.5 v with undervoltage lockout (uvlo) at v in = 2.0 v small wafer level chip scale package (wlcsp) or lead frame chip scale package (lfcsp) applications mobile display backlighting mobile phone keypad backlighting dual rgb backlighting led indication general backlighting of small format displays general description the ADP8860 combines a programmable backlight led charge pump driver with automatic phototransistor control. this combi- nation allows for significant power savings because it changes the current intensity in office and dark ambient light conditions. by performing this function automatically, it eliminates the need for a processor to monitor the phototransistor. the light intensity thresholds are fully programmable via the i 2 c? interface. a second phototransistor input, with dedicated comparators, improves the ambient light detection levels for various user operating conditions. typical operating circuit v d3 d1 e3 d2 e4 d3 d4 d4 c4 d5 b4 d6/ cmp_in2 b3 d7 als v out optional photosensor photosenso c3 cmp_in r 0.1f 0.1f v in a3 1f e1 vddio nrst c2 vddio sda e2 vddio scl d2 vddio nint a4 gnd1 d1 gnd2 b1 c2+ b2 c2? c2 1f a1 c1+ c1 c1? c1 1f v out a2 ADP8860 1f figure 1. the ADP8860 allows as many as six leds to be independently driven up to 30 ma (typical). a seventh led can be driven to 60 ma (typical). all leds are programmable for minimum/max- imum current and fade in/out times via the i 2 c interface. these leds can also be combined into groups to reduce the processor instructions during fade in/out. driving this entire configuration is a two-capacitor charge pump with gains of 1, 1.5, and 2. this setup is capable of driving a maximum i out of 240 ma from a supply of 2.5 v to 5.5 v. the device includes a variety of safety features including short-circuit, overvoltage, and overtemperature protection. these features allow easy implementation of a safe and robust design. addi- tionally, input inrush currents are limited via an integrated soft start combined with controlled input-to-output isolation. the ADP8860 is available in two package types, either a compact 2 mm 2.4 mm 0.6 mm wlcsp (wafer level chip scale package) or a small lfcsp (lead frame chip scale package).
ADP8860 rev. 0 | page 2 of 52 table of contents features .............................................................................................. 1 applications ....................................................................................... 1 general description ......................................................................... 1 typical operating circuit ................................................................ 1 revision history ............................................................................... 2 specifications ..................................................................................... 3 i 2 c timing diagram ..................................................................... 5 absolute maximum ratings ............................................................ 6 maximum temperature ranges ................................................. 6 thermal resistance ...................................................................... 6 esd caution .................................................................................. 6 pin configurations and function descriptions ........................... 7 typical performance characteristics ............................................. 8 theory of operation ...................................................................... 12 power stage.................................................................................. 13 operating modes ........................................................................ 14 backlight operating levels ....................................................... 16 backlight maximum and dim settings ................................... 17 automated fade in and fade out ............................................ 17 backlight turn on/turn off/dim ........................................... 17 automatic dim and turn off timers ..................................... 18 fade override ............................................................................. 19 ambient light sensing .............................................................. 19 automatic backlight adjustment ............................................. 20 independent sink control ........................................................ 20 short-circuit protection mode ................................................ 21 overvoltage protection .............................................................. 21 thermal shutdown/overtemperature protection ................. 21 interrupts ..................................................................................... 23 applications information .............................................................. 24 layout guidelines....................................................................... 24 example circuits ........................................................................ 25 i 2 c programming and digital control ........................................ 26 backlight register descriptions ............................................... 30 independent sink register descriptions ................................. 37 comparator register descriptions .......................................... 45 outline dimensions ....................................................................... 49 ordering guide .......................................................................... 50 revision history 5/09revision 0: initial version
ADP8860 rev. 0 | page 3 of 52 specifications vin = 3.6 v, scl = 2.7 v, sda = 2.7 v, nint = open, nrst = 2.7 v, cmp_in = 0 v, v d1:d7 = 0.4 v, c1 = 1 f, c2 = 1 f, c out = 1 f, typical values are at t a = 25c and are not guaranteed, minimum and maximum limits are guaranteed from t a = ?40c to +85c, unless otherwise noted. table 1. parameter symbol test conditions/comments min typ max unit supply input voltage operating range v in 2.5 5.5 v startup level v in(start) v in increasing 2.05 2.30 v low level v in(stop) v in decreasing 1.75 1.97 v v in(start) hysteresis v in(hys) after startup 80 mv uvlo noise filter t uvlo 10 s quiescent current i q prior to v in(start) i q(start) v in = v in(start) ? 100 mv 10 a during standby i q(stby) v in = 3.6 v, bit nstby = 0, scl = sda = 0 v 0.3 1.0 a after startup and switching i q(active) v in = 3.6 v, bit nstby = 1, i out = 0 ma, gain = 2 4.5 7.2 ma oscillator switching frequency f sw 0.8 1 1.32 mhz duty cycle d 50 % ouput current control maximum drive current i d1:d7(max) v d1:d7 = 0.4 v d1 to d7 bit scr = 0 in the isc7 register t j = 25c 26.2 30 34.1 ma t j = ?40c to +85c 24.4 34.1 ma d7 only (60 ma setting) i d7(60 ma) v d7 = 0.4 v, bit scr = 1 in the isc7 register t j = 25c 52.5 60 67 ma t j = ?40c to +85c 48.8 67 ma led current source matching 1 i match all current sinks i match7 v d1:d7 = 0.4 v 2.0 % d2 to d7 current sinks i match6 v d2:d7 = 0.4 v 1.5 % leakage current on led pins i d1:d7(lkg) v in = 5.5 v, v d1:d7 = 2.5 v, bit nstby = 1 0.5 a equivalent output resistance r out gain = 1 v in = 3.6 v, i out = 100 ma 0.5 gain = 1.5 v in = 3.1 v, i out = 100 ma 3.0 gain = 2 v in = 2.5 v, i out = 100 ma 3.8 regulated output voltage v out(reg) v in = 3 v, gain = 2, i out = 10 ma 4.3 4.9 5.5 v automatic gain selection minimum voltage gain increases v hr(up) decrease v d1:d7 until the gain switches up 162 200 276 mv minimum current sink headroom voltage v hr(min) i dx = i dx(max) 95% 180 mv gain delay t gain the delay after gain has changed and before gain is allo wed to change again 100 s
ADP8860 rev. 0 | page 4 of 52 parameter symbol test conditions/comments min typ max unit ambient light sensing comparators ambient light sensor current i als cmp_in = v d6 = 2.8 v, bit cmp2_sel = 1 0.70 1.08 1.33 ma dac bit step threshold l2 level i l2bit i l2bit = i als /250 4.3 a threshold l3 level i l3bit i l3bit = i als /2000 0.54 a fault protection startup charging current source i ss v in = 3.6 v, v out = 0.8 v in 2.5 3.75 5.5 ma output voltage threshold v out exit soft start v out(start) v out rising 0.92 v in v short-circuit protection v out(sc) v out falling 0.55 v in v output overvoltage protection v ovp activation level 5.8 v ovp recovery hysteresis 500 mv thermal shutdown threshold tsd 150 c hysteresis tsd (hys) 20 c isolation from input to output during fault i outlkg v in = 5.5 v, v out = 0 v, bit nstby = 0 1.5 a time to validate a fault t fault 2 s i 2 c interface v ddio voltage operating range v ddio 5.5 v logic low input 2 v il v in = 3.6 v 0.6 v logic high input 3 v ih v in = 3.6 v 1.30 v i 2 c timing specifications guaranteed by design delay from reset deassertion to i 2 c access t reset 20 s scl clock frequency f scl 400 khz scl high time t high 0.6 s scl low time t low 1.3 s setup time data t su, dat 100 ns repeated start t su, sta 0.6 s stop condition t su, sto 0.6 s hold time data t hd, dat 0 0.9 s start/repeated start t hd, sta 0.6 s bus free time (stop and start conditions) t buf 1.3 s rise time (scl and sda) t r 20 + 0.1 c b 300 ns fall time (scl and sda) t f 20 + 0.1 c b 300 ns pulse width of suppressed spike t sp 0 50 ns capacitive load per bus line c b 400 pf 1 current source matching is calc ulated by dividing the differe nce between the maximum and minimum current from the sum of the m aximum and minimum. 2 v il is a function of the input voltage. see in the section for typical values over o perating ranges. figure 16 figure 16 typical performance characteristics typical performance characteristics 3 v ih is a function of the input voltage. see in the section for typical values over o perating ranges.
ADP8860 rev. 0 | page 5 of 52 i 2 c timing diagram s d a scl s s = start condition sr = repeated start condition p = stop condition sr p s t low t r t hd, dat t high t su, dat t f t f t su, sta t hd, sta t sp t su, sto t buf t r 07967-002 figure 2. i 2 c interface timing diagram
ADP8860 rev. 0 | page 6 of 52 absolute maximum ratings thermal resistance table 2. parameter rating vin, vout ?0.3 v to +6 v d1, d2, d3, d4, d5, d6, and d7 ?0.3 v to +6 v cmp_in ?0.3 v to +6 v nint, nrst, scl, and sda ?0.3 v to +6 v output short-circuit duration indefinite operating ambient temperature range C40c to +85c 1 operating junction temperature range C40c to +125c storage temperature range C65c to +150c soldering conditions jedec j-std-020 esd (electrostatic discharge) human body model (hbm) 2 kv charged device model (cdm) 2 kv ja (junction to air) is specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. the ja , jb (junction to board), and jc (junction to case) are determined according to jesd51-9 on a 4-layer printed circuit board (pcb) with natural convection cooling. for the lfcsp package, the exposed pad must be soldered to the gnd1 and/or gnd2 terminal(s) on the board. table 3. thermal resistance 1 package type ja jb jc unit wlcsp 48 9 n/a c/w lfcsp_vq 49.5 n/a 5.3 c/w 1 n/a means not applicable. 1 the maximum operating junction temperature (t j(max) ) supersedes the maximum operating ambient temperature (t a(max) ). see the maximum temperature ranges section for more information. esd caution stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings apply individually only, not in combination. unless otherwise specified, all voltages are referenced to gnd. maximum temperature ranges the maximum operating junction temperature (t j(max) ) supersedes the maximum operating ambient temperature (t a(max) ). therefore, in situations where the ADP8860 is exposed to poor thermal resistance and a high power dissipation (p d ), the maximum ambient temperature may need to be derated. in these cases, the ambient temperature maximum can be calculated with the following equation: t a(max) = t j(max) ? ( ja p d(max) )
ADP8860 rev. 0 | page 7 of 52 pin configurations and function descriptions pin 1 indicator 1 d3 2 d2 3 d1 4 scl 5 nrst 13 vout 14 vin 15 gnd1 12 c2+ 11 c1+ 6 nint 7 sda 8 g nd2 10 c2? 9 c1? 18 cmp_in 19 d5 20 d4 17 d6/cmp_in2 16 d7 top view (not to scale) ADP8860 notes 1. connect the exposed paddle to gnd1 and/or gnd2. 0 7967-003 07967-004 top view (ball side down) not to scale ADP8860 1 a b c d 234 figure 3. lfcsp pin configuration c1+ c1? c2+ gnd2 nrst vin d7 cmp_in d1 d2 gnd1 vout d5 d6/ cmp_in2 sda c2? nint d4 d3 scl e figure 4. wlcsp pin configuration table 4. pin function descriptions pin no. mnemonic description lfcsp wlcsp 14 a3 vin input voltage 2.5 v to 5.5 v. 3 d3 d1 led sink 1. 2 e3 d2 led sink 2. 1 e4 d3 led sink 3. 20 d4 d4 led sink 4. 19 c4 d5 led sink 5. 17 b4 d6/cmp_in2 led sink 6/comparator input for second phototransistor. when using this pin as a second phototransistor input, a capacitor (0.1 f recommende d) must be connected from this pin to ground. 16 b3 d7 led sink 7. 18 c3 cmp_in comparator input for phototransistor. when us ing this function, a capacitor (0.1 f recommended) must be connected from this pin to ground. 13 a2 vout charge pump output. 11 a1 c1+ charge pump c1+. 9 c1 c1? charge pump c1?. 12 b1 c2+ charge pump c2+. 10 b2 c2? charge pump c2?. 15 a4 gnd1 ground. connect the exposed pad to gnd1 and/or gnd2. 8 d1 gnd2 ground. connect the exposed pad to gnd1 and/or gnd2. 6 d2 nint processor interrupt (active low). requires an external pull-up resistor. if this pin is not used, it can be left floating. 5 e1 nrst hardware reset (active low). this bit resets th e device to the default conditions. if not used, this pin must be tied above v ih(min) . 7 c2 sda i 2 c serial data. requires an external pull-up resistor. 4 e2 scl i 2 c clock. requires an external pull-up resistor.
ADP8860 rev. 0 | page 8 of 52 typical performance characteristics vin = 3.6 v, scl = 2.7 v, sda = 2.7 v, nrst = 2.7 v, v d1:d7 = 0.4 v, c in = 1 f, c1 = 1 f, c2 = 1 f, c out = 1 f, t a = 25c, unless otherwise noted. 2.0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i q (ma) v in (v) +25c +85c +105c ?40c i out = no load 07967-100 figure 5. typical operating current, g = 1 5.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i q (ma) v in (v) +25c +85c +105c ?40c i out = no load 07967-101 figure 6. typical operating current, g = 2, i q(active) 10 1 0.1 0.01 0.001 1 0 23456 i q (a) v in (v) +25c +85c +105c ?40c scl = sda = 0v nrst = 2.7v 07967-102 figure 7. typical standby i q 35 30 25 20 15 10 5 0 0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 i out (ma) v hr (v) v in = 3.6v i d1:d7 = 30ma d1 d2 d3 d4 d5 d6 d7 07967-103 figure 8. typical diode current vs. current sink headroom voltage (v hr ) 35 34 33 32 31 30 29 28 27 26 25 2.0 5.5 2.5 3.0 3.5 4.0 4.5 5.0 i out (ma) v in (v) v d1:d7 = 0.4v d1 d2 d3 d4 d5 d6 d7 07967-104 figure 9. typical diode matching vs. v in 6 0 1 2 3 4 5 0.2 2.01.81.61.41.21.0 0.8 0.60.4 mismatch (%) v hr (v) +25c +85c +105c ?40c v in = 3.6v i d1:d7 = 30ma 07967-105 figure 10. typical diode matching vs. current sink headroom voltage (v hr )
ADP8860 rev. 0 | page 9 of 52 35 5 10 15 20 25 30 v in = 3.6v i d1:d7 = 30ma 0 i out (ma) 00.2 2.0 1.81.6 1.41.21.00.80.60.4 v hr (v) ?40c +25c +85c +105c 07967-10 6 figure 11. typical diode current vs . current sink headroom voltage (v hr ) 1 ?5 ?4 ?3 ?2 ?1 0 v in = 3.6v v d1:d7 = 0.40v ?6 i out deviation (%) ?40 ?10 20 50 80 110 junction temperature (c) 07967-1 07 figure 12. typical change in diode current vs. temperature 7 6 5 4 3 2 1 r out ( ? ) 0 ?40 ?20 0 20 40 60 80 100 temperature (c) i out = 100ma g = 1 @ v = 3.6v g = 1.5 @ v in = 3v g = 2 @ v in = 2.5v in 07967-108 figure 13. r out vs. temperature 1.0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 r out ( ? ) v in (v) +25c +85c +105c ?40c i out = 100ma 07967-109 figure 14. typical rout (g = 1) vs. v in 10 9 8 7 6 5 4 3 2 1 0 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 i out (ma) v in (v) +25c +85c +105c ?40c v out = 80% of v in 07967-110 figure 15. typical soft start current, i ss 1.4 1.2 1.0 0.8 0.6 0.4 0.2 0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 threshold (v) v in (v) v il = +25c v il = +85c v il = ?40c v ih = +25c v ih = +85c v ih = ?40c 07967-111 figure 16. typical i 2 c thresholds, v ih and v il
ADP8860 rev. 0 | page 10 of 52 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 i als (ma) 3.0 2.5 3.5 4.0 4.5 5.0 5.5 v in (v) ?40c +25c +85c +105c 07967-11 2 figure 17. typical als current, i als 5.5 4.7 4.8 4.9 5.0 5.1 5.2 5.3 5.4 v in = 3v gain = 2 i out = 10ma 4.5 4.6 v out (v) ?10 ?40 20 50 80 110 junction temperature (c) 07967-1 13 figure 18. typical regulated output voltage (v out(reg) ) 6.0 5.8 5.6 5.4 v out (v) 5.2 ?10 ?40 20 50 80 110 junction temperature (c) ovp threshold ovp recovery 07967-114 figure 19. typical overvoltage protection (ovp) threshold 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 450 400 350 300 250 200 150 100 50 0 2.5 5.5 5.0 4.5 4.0 3.5 3.0 efficiency (%) i in (ma) v in (v) i out = 140ma, vf = 3.1v i out = 210ma, vf = 3.2v 07967-115 figure 20. typical efficiency (low vf diode) 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 450 400 350 300 250 200 150 100 50 0 2.5 5.5 5.0 4.5 4.0 3.5 3.0 efficiency (%) i in (ma) v in (v) i out = 140ma, vf = 3.85v i out = 210ma, vf = 4.25v 07967-116 figure 21. typical efficiency (high vf diode) 1 3 t 500ns/div v in (ac-coupled) 50mv/div v out (ac-coupled) 50mv/div i in (ac-coupled) 10ma/div c in = 1f, c out = 1f, c1 = 1f, c2 = 1f v in = 3.6v i out = 120ma 07967-117 2 figure 22. typical operat ing waveforms, g = 1
ADP8860 rev. 0 | page 11 of 52 t v in (ac-coupled) 50mv/div 1 v out (ac-coupled) 50mv/div 2 i in (ac-coupled) 10ma/div 3 500ns/div c in = 1f, c out = 1f, c1 = 1f, c2 = 1f v in = 3.0v i out = 120ma 0796 7-118 figure 23. typical operating waveforms, g = 1.5 t v in (ac-coupled) 50mv/div 1 v out (ac-coupled) 50mv/div 2 i in (ac-coupled) 10ma/div 3 c in = 1f, c out = 1f, c1 = 1f, c2 = 1f v in = 2.5v i out = 120ma 500ns/div 07967-119 figure 24. typical operat ing waveforms, g = 2 2 4 100s/div i out (10ma/div) v out (1v/div) i in (10ma/div) v in = 3.7v 07967-120 figure 25. typical start-up waveform
ADP8860 rev. 0 | page 12 of 52 theory of operation the ADP8860 combines a programmable backlight led charge pump driver with automatic phototransistor control. this combi- nation allows for significant power savings because it is able to change the current intensity based on the lighting conditions. it performs this function automatically thereby removing the need for a processor to monitor the phototransistor. the light intensity levels are fully programmable via the i 2 c interface. a second phototransistor input, with dedicated comparators, improves the ambient light detection abilities for various user- operating conditions. the ADP8860 allows up to seven leds to be independently driven up to 30 ma (typical). the seventh led can also be driven to 60 ma (typical). all leds can be individually pro- grammed or combined into a group to operate backlight leds. a full set of safety features including short-circuit, overvoltage, and overtemperature protection with input-to-output isolation allow for a robust and safe design. the integrated soft start limits inrush currents at startup, restart attempts, and gain transitions. c1 1f c2 1f gnd2 d1 nint cmp_in c3 d2 c out vout a2 c in vin v refs i refs stndby en vin vbat c1+ sda c2 scl e2 i 2 c logic vddio stndby switch control iled control a1 c1 b1 b2 c1? c2+ c2? nrst e1 noise filter 50s reset a3 d2 e3 d3 e4 d4 d4 d5 c4 d6 b4 d7 b3 d1 d3 v als optional photosensor id1 id2 id3 id4 id5 id6 id7 gain select logic charge pump logic v in light sensor logic gnd1 a4 clk uvlo photosensor conversion charge pump (1, 1.5, 2) soft start 07967-011 i ss figure 26. detailed block diagram
ADP8860 rev. 0 | page 13 of 52 power stage because typical white leds require up to 4 v to drive them, some form of boosting is required over the typical variation in battery voltage. the ADP8860 accomplishes this with a high efficiency charge pump capable of producing a maximum i out of 240 ma over the entire input voltage range (2.5 v to 5.5 v). charge pumps use the basic principle that a capacitor stores charge based on the voltage applied to it, as shown in the following equation: q = c v (1) by charging the capacitors in different configurations, the charge, and therefore the gain, can be optimized to deliver the voltage required to power the leds. because a fixed charging and discharging combination must be used, only certain multiples of gain are available. the ADP8860 is capable of automatically optimizing the gain (g) from 1, 1.5, and 2. these gains are accomplished with two capacitors (labeled c1 and c2 in figure 26 ) and an internal switching network. in g = 1 mode, the switches are configured to pass vin directly to vout. in this mode, several switches are connected in parallel to minimize the resistive drop from input to output. in g = 1.5 and 2 modes, the switches alternatively charge from the battery and discharge into the output. for g = 1.5, the capacitors are charged from vin in series and are discharged to vout in parallel. for g = 2, the capacitors are charged from vin in parallel and are discharged to vout in parallel. in certain fault modes, the switches are opened and the output is physically isolated from the input. automatic gain selection each led that is driven requires a current source. the voltage on this current source must be greater than a minimum head- room voltage (200 mv typical) to maintain accurate current regulation. the gain is automatically selected based on the minimum voltage (v dx ) at all of the current sources. at startup, the device is placed into g = 1 mode and the output charges to v in . if any v dx level is less than the required headroom (200 mv), the gain is increased to the next step (g = 1.5). a 100 s delay is allowed for the output to stabilize prior to the next gain switching decision. if there remains insufficient current sink headroom, then the gain is increased again to 2. conversely, to optimize efficiency, it is not desirable for the output voltage to be too high. therefore, the gain reduces when the headroom voltage is great enough. this point (labeled v dmax in figure 27 ) is internally calculated to ensure that the lower gain still results in ample headroom for all the current sinks. the entire cycle is illustrated in figure 27 . note that the gain selection criteria apply only to active current sources. if current sources have been deactivated through an i 2 c command (for example, only five leds are used), then the voltages on the deactivated current sources are ignored.
ADP8860 rev. 0 | page 14 of 52 07967-012 notes 1. v dmax is the calculated gain down transition point. wait 100s (typ) min (v d1:d7 ) < v hr(up) 0 0 1 1 1 1 0 0 statup: charge v in to v out exit stby vout > v out(start) 1 wait 100s (typ) wait 100s (typ) min (v d1:d7 ) < v hr(up) min (v d1:d7 ) > v dmax min (v d1:d7 ) < v dmax g = 2 g = 3/2 exit startup g = 1 stby 0 figure 27. state diagram for automatic gain selection soft start feature at startup (either from uvlo activation or fault/standby recovery), the output is first charged by i ss (3.75 ma typical) until it reaches about 92% of v in . this soft start feature reduces the inrush current that is otherwise present when the output capacitance is initially charged to v in . when this point is reached, the controller enters 1 mode. if the output voltage is not sufficient, then the automatic gain selection determines the optimal point as defined in the automatic gain selection section. operating modes there are four different operating modes: active, standby, shutdown, and reset. active mode in active mode, all circuits are powered up and in a fully operational state. this mode is entered when nstby (in register mdcr) is set to 1. standby mode standby mode disables all circuitry except for the i 2 c receivers. current consumption is reduced to less than 1 a. this mode is entered when nstby is set to 0 or when the nrst pin is held low for more than 100 s (maximum). when standby is exited, a soft start sequence is performed. shutdown mode shutdown mode disables all circuitry, including the i 2 c receivers. shutdown occurs when v in is below the undervoltage thresholds. when v in rises above v in(start) (2.05 v typical), all registers are reset and the part is placed into standby mode. reset mode in reset mode, all registers are set to their default values and the part is placed into standby. there are two ways to reset the part: power-on reset (por) and the nrst pin. por is activated any- time that the part exits shutdown mode. after a por sequence is complete, the part automatically enters standby mode. after startup, the part can be reset by pulling the nrst pin low. as long as the nrst pin is low, the part is held in a standby state but no i 2 c commands are acknowledged (all registers are kept at their default values). after releasing the nrst pin, all registers remain at their default values, and the part remains in standby; however, the part does accept i 2 c commands. the nrst pin has a 50 s (typical) noise filter to prevent inad- vertent activation of the reset function. the nrst pin must be held low for this entire time to activate reset. the operating modes function according to the timing diagram in figure 28 .
ADP8860 rev. 0 | page 15 of 52 v in nstby nrst v out v in shutdown v in crosses ~2.05v and triggers power on reset bit nstby in register mdcr goes high nrst must be high for 20s (max) before sending i 2 c commands nrst is low, which forces nstby low and resets all i 2 c registers gain changes only occur when necessary, ~100s delay between power up and when i 2 c commands can be received ~3.75ma charges v out to v in level 25s to 100s noise filter but have a min time before changing 1 1.5 2 soft start soft start 10s 100s 0 7967-013 figure 28. typical timing diagram
ADP8860 rev. 0 | page 16 of 52 backlight operating levels backlight brightness control operates in three distinct levels: daylight (l1), office (l2), and dark (l3). the blv bits in register 0x04 control the specific level in which the backlight operates. these bits can be changed manually, or if in automatic mode (cmp_autoen is set high in register 0x01), by the ambient light sensor (see the ambient light sensing section). by default, the backlight operates at daylight level (blv = 00), where the maximum brightness is set using register 0x09 (blmx1). a daylight dim setting can also be set using register 0x0a (bldm1). when operating at office level (blv = 01), the backlight maximum and dim brightness settings are set by register 0x0b (blmx2) and register 0x0c (bldm2). when operating at the dark level (blv = 10), the backlight maximum and dim brightness settings are set by register 0x0d (blmx3) and register 0x0e (bldm3). d a ylight (l1) office (l2) dark (l3) ht current daylight_max office_max backlight operating levels backlig daylight_dim dark_max dark_dim office_dim 0 07967-014 30ma figure 29. backlight operating levels
ADP8860 rev. 0 | page 17 of 52 backlight maximum and dim settings the backlight maximum and dim current settings are deter- mined by a 7-bit code programmed by the user into the registers previously listed in the backlight operating levels section. the 7-bit resolution allows the user to set the backlight to one of 128 different levels between 0 ma and 30 ma. the ADP8860 can implement two distinct algorithms to achieve a linear and a nonlinear relationship between input code and backlight current. the law bits in register 0x04 are used to change between these algorithms. by default, the ADP8860 uses a linear algorithm (law = 00), where the backlight current increases linearly for a corresponding increase of input code. backlight current (in millamperes) is determined by the following equation: backlight current (ma) = code ( full-scale current /127) (2) where: code is the input code programmed by the user. full-scale current is the maximum sink current allowed per led (typically 30 ma). the ADP8860 can also implement a nonlinear (square approxima- tion) relationship between input code and backlight current level. in this case (law = 01), the backlight current (in milliamperes) is determined by the following equation: 2 127 )ma( ? ? ? ? ? ? ? = current scalefull code current backlight ? ? (3) figure 30 shows the backlight current level vs. input code for both the linear and square law algorithms. 30 25 20 15 10 5 backlight current (ma) 0 0 32 64 96 128 sink code linear square 07967-015 figure 30. backlight current vs. input code automated fade in and fade out the led drivers are easily configured for automated fade in and fade out. sixteen fade in and fade out rates can be selected via the i 2 c interface. fade in and fade out rates range from 0.1 sec to 5.5 sec (per full-scale current, either 30 ma or 60 ma). table 5. available fade in and fade out rates code fade rate (in sec per full-scale current) 0000 0.1 (disabled) 0001 0.3 0010 0.6 0011 0.9 0100 1.2 0101 1.5 0110 1.8 0111 2.1 1000 2.4 1001 2.7 1010 3.0 1011 3.5 1100 4.0 1101 4.5 1110 5.0 1111 5.5 the fade profile is based on the transfer law selected (linear, square, cubic 10, or cubic 11) and the delta between the actual current and the target current. smaller changes in current reduce the fade time. for linear and square law fades, the fade time is given by fade time = fade rate ( code /127) (4) where the fade rate is shown in tabl e 5 . the cubic 10 and cubic 11 laws also use the square backlight currents in equation 3; however, the time between each step is varied to produce a steeper slope at higher currents and a shallower slope at lighter currents (see figure 31 ). 30 0 5 10 15 20 25 01 0.75 0.50 0.25 current (ma) unit fade time . 0 0 linear square cubic 11 cubic 10 07967-016 figure 31. comparison of the dimming transfers laws backlight turn on/turn off/dim with the device in active mode (nstby = 1), the backlight can be turned on using the bl_en bit in register 0x01. before turning on the backlight, the user chooses which level (daylight (l1), office (l2), or dark (l3)) in which to operate, and ensures that maximum and dim settings are programmed for that level.
ADP8860 rev. 0 | page 18 of 52 the backlight turns on when bl_en = 1. the backlight turns off when bl_en = 0. max backlight current bl_en = 1 bl_en = 0 0 7967-017 figure 32. backlight turn on/off while the backlight is on (bl_en = 1), the user can change to the dim setting by programming dim_en = 1 in register 0x01. if dim_en = 0, the backlight reverts to its maximum setting. max dim backlight current bl_en = 1 dim_en = 1 dim_en = 0 bl_en = 0 0 7967-018 figure 33. backlight turn on/dim/turn off the maximum and dim settings can be set between 0 ma and 30 ma; therefore, it is possible to program a dim setting that is greater than a maximum setting. for normal expected opera- tion, ensure that the dim setting is programmed to be less than the maximum setting. automatic dim and turn off timers the user can program the backlight to dim automatically by using the dimt timer in register 0x07. the dim timer has 127 settings ranging from 1 sec to 127 sec. program the dim timer (dimt) before turning on the backlight. if bl_en = 1, the backlight turns on to its maximum setting and the dim timer starts counting. when the dim timer expires, the internal state machine sets dim_en = 1, and the backlight enters its dim setting. max dim bl_en = 1 bl_en = 0 dim_en = 1 dim_en = 0 dim_en = 1 backlight current dim timer running dim timer running set by user set by internal statemachine 0 7967-019 figure 34. dim timer if the user clears the dim_en bit, the backlight reverts to its maximum setting and the dim timer begins counting again. when the dim timer expires, the internal state machine again sets dim_en = 1, and the backlight enters its dim setting. the backlight can be turned off at any point during the dim timer countdown by clearing bl_en. the user can also program the backlight to turn off automati- cally by using the offt timer in register 0x06. the off timer has 127 settings ranging from 1 sec to 127 sec. program the off timer (offt) before turning on the backlight. if bl_en = 1, the backlight turns on to its maximum setting and the off timer starts counting. when the off timer expires, the internal state machine clears the bl_en bit, and the backlight turns off. max bl_en = 1 bl_en = 0 backlight current off timer running set by user set by internal state machine 07967-020 figure 35. off timer the backlight can be turned off at any point during the off timer countdown by clearing bl_en. the dim timer and off timer can be used together for sequential maximum-to-dim-to-off functionality. with both the dim and off timers programmed, if bl_en is asserted, the backlight turns on to its maximum setting, and when the dim timer expires, the backlight changes to its dim setting. when the off timer expires, the backlight turns off.
ADP8860 rev. 0 | page 19 of 52 max dim backlight current bl_en = 1 bl_en = 0 dim_en = 1 dim timer running off timer running set by user set by internal state machine 07967-021 figure 36. dim and off timers used together fade override a fade override feature (fovr in register cfgr (0x04)) enables the host to override the preprogrammed fade in or fade out settings. if fovr is set and the backlight is enabled in the middle of a fade out process, the backlight instantly (within approximately 100 ms) returns to its maximum setting. alter- natively, if the backlight is fading in, reasserting bl_en overrides the programmed fade in time and the backlight instantly goes to its final fade value. this is useful for situations where a key is pressed during a fade sequence. however, if fovr is cleared and the backlight is enabled in the middle of a fade process, the backlight gradually brightens from where it was interrupted (it does not go down to 0 and then come back on). max backlight current fade-in over-ridden fade-out over-ridden bl_en = 1 bl_en = 0 bl_en = 1 bl_en = 0 bl_en = 1 (re-asserted) 07967-022 figure 37. fade override function (fovr is high) ambient light sensing the ADP8860 integrates two ambient light sensing comparators. one of the ambient light sensing comparator pins (cmp_in) is always available. the second pin (d6/cmp_in2) can be activated rather than connecting an led to d6. activating the cmp_in2 function of the pin is accomplished through bit cmp2_sel in register cfgr. therefore, when bit cmp2_sel is set to 0, pin d6/cmp_in2 is programmed as a current sink. when bit cmp2_sel is set to 1, pin d6/cmp_in2 becomes the input for a second phototransistor. these comparators have two programmable trip points (l2 and l3) that select among three of the backlight operation modes (daylight, office, and dark) based on the ambient lighting conditions. the l3 comparator controls the dark-to-office mode transition. the l2 comparator controls the office-to-daylight transition (see figure 38 ). the currents for the different lighting modes are defined in the blmxx and bldmx registers (see the backlight operating levels section). brightness l3 l2 dark office daylight 0 lux 0a l2_out = 1 l3_out = 1 l2_out = 1 l3_out = 0 l2_out = 0 l3_out = 0 07967-023 figure 38. light sensor modes based on the detected ambient light level each light sensor comparator uses an external capacitor together with an internal reference current source to form an analog-to- digital converter (adc) that samples the output of the external photosensor. the adc result is fed into two programmable trip comparators. the adc has an input range of 0 a to 1080 a (typical). l2_hys l2_trip l3_trip l3_hys filter settings adc photo sensor output l2_en l3_en l2_out l3_out 07967-024 figure 39. ambient light sensing and trip comparators the l2_cmpr detects when the photosensor output has dropped below the programmable l2_trp point (register 0x1d). if this event occurs, then the l2_out status signal is set. l2_cmpr contains programmable hysteresis, meaning that the photo- sensor output must rise above l2_trp + l2_hys before l2_out clears. l2_cmpr is enabled via the l2_en bit. the l2_trp and l2_hys values of l2_cmpr can be set between 0 a and 1080 a (typical) in steps of 4.3 a (typical). the l3_cmpr detects when the photosensor output has dropped below the programmable l3_trp point (register 0x1f). if this event occurs, the l3_out status signal is set. l3_cmpr
ADP8860 rev. 0 | page 20 of 52 contains programmable hysteresis, meaning that the photo- sensor output must rise above l3_trp + l3_hys before l3_out clears. l3_cmpr is enabled via the l3_en bit. the l3_trp and l3_hys values of l3_cmpr can be set between 0 a and 137.7 a (typical) in steps of 0.54 a (typical). l2_trp l2_hys l3_trp l3_hys 1 10 100 1000 adc range (a) 07967-025 figure 40. comparator ranges note that the full-scale value of the l2_trp and l2_hys registers is 250 (decimal). therefore, if the value of l2_trp + l2_hys exceeds 250, the comparator output is unable to deassert. for example, if l2_trp is set at 204 (80% of the full- scale value, or approximately 0.80 1080 a = 864 a), then l2_hys must be set at less than 46 (250 ? 204 = 46). if it is not, then the l2_hys + l2_trp exceeds 250 and the l2_cmpr comparator is never allowed to go low. when both phototransistors are enabled and programmed in automatic mode (through bit l3_en and bit l2_en in register 0x1b and register 0x1c), the user application needs to determine which of the comparator outputs to use, selecting bit sel_ab in register 0x04 for automatic light sensing transitions. for example, the users software may select the comparator of the phototransistor exposed to higher light intensity to control the transition between the programmed backlight intensity levels. the l2_cmpr and l3_cmpr comparators can be enabled independently of each other, or can operate simultaneously. a single conversion from each adc takes 80 ms (typical). when cmp_autoen is set for automatic backlight adjustment (see the automatic backlight adjustment section), the adc and comparators run continuously. if the backlight is disabled and at least one independent sink is enabled, it is possible to use the light sensor comparators in a single shot mode. a single shot read of the photocomparators is performed by setting the force_rd bit. after the single shot measurement is completed, the internal state machine clears the force_rd bit. the interrupt flags (cmp_int and cmp_int2) can be used to notify the system when either l2 or l3 changes state. refer to the interrupts section for more information. automatic backlight adjustment the ambient light sensor comparators can automatically transition the backlight between one of its three operating levels. to enable this mode, set the cmp_autoen bit in register 0x01. when enabled, the internal state machine takes control of the blv bits and changes them based on the l2_out and l3_out status bits. when l2_out is set high, it indicates that the ambient light conditions have dropped below the l2_trp point and the backlight should move to its office (l2) level. when l3_out is set high, it indicates that ambient light conditions have dropped below the l3_trp point and the backlight should move to its dark (l3) level. tabl e 6 shows the relationship between backlight operation and the ambient light sensor comparator outputs. the l3_out status bit has greater priority; therefore, the backlight operates at l3 (dark) even if l2_out is set. filter times of between 80 ms and 10 sec can be programmed for the comparators (register 0x1b and register 0x1c) before they change state. table 6. comparator output truth table cmp_autoen l3_out l2_out backlight operation 0 x 1 x 1 blv can be manually set by the user 1 0 0 blv = 00, backlight operates at l1 (daylight) 1 0 1 blv = 01, backlight operates at l2 (office) 1 1 x 1 blv = 10, backlight operates at l3 (dark) 1 x is the dont care bit. independent sink control each of the seven leds can be configured (in register 0x05) to operate as either part of the backlight or to operate as an indepen- dent sink current (isc). each isc can be enabled independently and has its own current level. all iscs share the same fade in rates, fade out rates, and fade law. the iscs have additional timers to facilitate blinking functions. a shared on timer (scon) used in conjunction with the off timers of each isc (sc1off, sc2off, sc3off, sc4off, sc5off, sc6off, and sc7off) allow the led current sinks to be configured in various blinking modes. the on timer can be set to four different settings: 0.2 sec, 0.6 sec, 0.8 sec, and 1.2 sec. the off timers have four different settings: disabled, 0.6 sec, 1.2 sec, and 1.8 sec. blink mode is activated by setting the off timers to any setting other than disabled.
ADP8860 rev. 0 | page 21 of 52 scx_en program all fade, on, and off timers before enabling any of the led current sinks. if iscx is on during a blink cycle and scx_en is cleared, it turns off (or fades to off if fade out is enabled). if iscx is off during a blink cycle and scx_en is cleared, it stays off. max scx current fade-in fade-out fade-in fade-out on time on time off time off time set by user 07967-026 figure 41. independent sink blink mode with fading short-circuit protection mode the ADP8860 can protect against short circuits on the output (vout). short-circuit protection (scp) is activated at the point when vout < 55% of v in . note that this scp sensing is disabled during both start-up and restart attempts (fault recovery). scp sensing reenables 4 ms (typical) after activation. during a short- circuit fault, the device enters a low current consumption state and an interrupt flag is set. the device can be restarted at any time after receiving a short-circuit fault by simply rewriting nstby = 1. it then repeats another complete soft start sequence. note that the value of the output capacitance (c out ) should be small enough to allow vout to reach approximately 55% (typical) of v in within the 4 ms (typical) time. if c out is too large, the device inadvertently enters short-circuit protection. overvoltage protection overvoltage protection (ovp) is implemented on the output. there are two types of overvoltage events: normal (no fault) and abnormal (from a fault or sudden load change). normal overvoltage in a normal (no fault) overvoltage, the output voltage approaches v out(reg) (4.9 v typical) during normal operation. this is not caused by a fault or load change, but it is simply a consequence of the input voltage times the gain reaching the same level as the clamped output voltage (v out(reg) ). to prevent this type of over- voltage, the ADP8860 detects when the output voltage rises to v out(reg) . it then increases the effective r out of the gain stage to reduce the voltage that is delivered. this effectively regulates v out to v out(reg) ; however, there is a limit to the effect that this system can have on regulating v out . it is designed only for normal operation and it is not intended to protect against faults or sudden load changes. when the output voltage is regulated to v out(reg) no interrupt is set and the operation is transparent to the leds and the overall application. abnormal overvoltage because of the open-loop behavior of the charge pump as well as how the gain transitions are computed, a sudden load change or fault can abnormally force v out beyond 6 v. this causes an abnormal overvoltage situation. if the event happens slowly enough, the system first tries to regulate the output to 4.9 v as in a normal overvoltage scenario. however, if this is not sufficient, or if the event happens too quickly, then the ADP8860 enters overvoltage protection (ovp) mode when v out exceeds the ovp threshold (typically 5.8 v). in the ovp mode, only the charge pump is disabled to prevent v out from rising too high. the current sources and all other device functionality remain intact. when the output voltage falls by about 500 mv (to 5.3 v typical), the charge pump resumes operation. if the fault or load step recurs, the process may repeat. an interrupt flag is set at each ovp instance. thermal shutdown/overtemperature protection if the die temperature of the ADP8860 rises above a safe limit (150c typical), the controllers enter thermal shutdown (tsd) protection mode. in this mode, most of the internal functions shut down, the part enters standby, and the tsd_int interrupt is set. when the die temperature decreases below ~130c, the part can be restarted. to restart the part, simply remove it from standby. no interrupt is generated when the die temperature falls below 130c. however, if the software clears the pending tsd_int interrupt and the temperature remains above 130c, another interrupt is generated. the complete state machine for these faults (scp, ovp, and tsd) is shown in figure 42 .
ADP8860 rev. 0 | page 22 of 52 wait 100s (typ) g = 2 g = 3/2 0 0 1 1 1 1 0 vout > v ovp ovp fault 1 0 1 0 v out > v out(reg) try to regulate vout to v out(reg) vout > v ovp ovp fault vout < v ovp ? v ovp (hys) 0 1 0 1 1 0 vout > v ovp ovp fault 0 1 0 1 1 0 exit startup g = 1 stby 1 0 vout < v out(sc) 0 scp fault exit stby startup: charge v in to v out v out > v out(start) die temp > tsd 0 tsd fault die temp < tsd ? tsd (hys) min (v d1:d7 ) < v hr(up) min (v d1:d7 ) < v hr(up) min (v d1:d7 ) > v dmax min (v d1:d7 ) > v dmax 1 0 exit stby wait 100s (typ) wait 100s (typ) vout < v ovp ? v ovp (hys) v out > v out(reg) try to regulate vout to notes vout < v ovp ? v ovp(hys) 1 v out(reg) 1. v dmax is the calculated gain down transition point. 07967-027 0 figure 42. fault state machine
ADP8860 rev. 0 | page 23 of 52 interrupts there are five interrupt sources available on the ADP8860. ? main light sensor comparator: cmp_int sets every time the main light sensor comparator detects a threshold (l2 or l3) transition (rising or falling conditions). ? sensor comparator 2: cmp2 _int interrupt works the same way as cmp_int, except the sensing input derives from the second light sensor. the programmable thresholds are the same as the main light sensor comparator. ? overvoltage protection: ovp_int is generated when the output voltage exceeds 5.8 v (typical). ? thermal shutdown circuit: an interrupt (tsd_int) is generated when entering overtemperature protection. ? short-circuit detection: short_int is generated when the device enters short-circuit protection mode. the interrupt (if any) that appears on the nint pin is deter- mined by the bits mapped in register intr_en. to clear an interrupt, write a 1 to the interrupt in the mdcr2 register or reset the part. reading the interrupt, or writing a 0, has no effect.
ADP8860 rev. 0 | page 24 of 52 07967-14 applications information the ADP8860 allows the charge pump to operate efficiently with a minimum of external components. specifically, the user must select an input capacitor (c in ), output capacitor (c out ), and two charge pump fly capacitors (c1 and c2). c in should be 1 f or greater. the value must be high enough to produce a stable input voltage signal at the minimum input voltage and maximum output load. a 1 f capacitor for c out is recommended. larger values are permissible, but care must be exercised to ensure that vout charges above 55% (typical) of v in within 4 ms (typical). see the short-circuit protection mode section for more details. for best practice, it is recommended that the two charge pump fly capacitors be 1 f; larger values are not recommended and smaller values may reduce the ability of the charge pump to deliver maximum current. for optimal efficiency, the charge pump fly capacitors should have low equivalent series resistance (esr). low esr x5r or x7r capacitors are recommended for all four components. use voltage ratings of 10 v or greater for these capacitors. if one or both ambient light sensor comparator inputs (cmp_in and d6/cmp_in2) are used, a small capacitor (0.1 f is recommended) must be connected from the input to ground. any color of led can be used if the vf (forward voltage) is less than 4.1 v. however, using lower vf leds reduces the input power consumption by allowing the charge pump to operate at lower gain states. the equivalent circuit model for a charge pump is shown in figure 43 . 0 v dx c out g v in r out v out i out figure 43. charge pump equivalent circuit model the input voltage is multiplied by the gain (g) and delivered to the output through an effective resistance (r out ). the output current flows through r out and produces an ir drop to yield v out = g v in ? i out r out ( g ) (5) the r out term is a combination of the r dson resistance for the switches used in the charge pump and a small resistance that accounts for the effective dynamic charge pump resistance. the r out level changes based upon the gain (the configuration of the switches). typical r out values are given in tabl e 1 and figure 13 and figure 14 . v out is also equal to the largest vf of the leds that are used plus the voltage drop across the regulating current source. this gives v out = vf (max) + v dx (6) combining equation 5 and equation 6 gives v i n = ( vf (max) + v dx + i out r out ( g ))/ g (7) this equation is useful for calculating approximate bounds for the charge pump design. determining the transition point of the charge pump consider the following design example where: vf (max) = 3.7 v i out = 140 ma (7 leds at 20 ma each) r out (g = 1.5) = 3 (obtained from figure 13 ) at the point of a gain transition, v dx = v hr(up) , table 1 gives the typical value of v hr(up) as 0.2 v. therefore, the input voltage level when the gain transitions from 1.5 to 2 is v in = (3.7 v + 0.2 v + 140 ma 3 )/1.5 = 2.88 v layout guidelines ? for optimal noise immunity, place the c in and c out capacitors as close as possible to their respective pins. these capacitors should share a short ground trace. if the leds are a significant distance from the vout pin, another capacitor on vout, placed closer to the leds, is advisable. ? for optimal efficiency, place the charge pump fly capacitors as close to the part as possible. ? the ADP8860 does not distinguish between power ground and analog ground. therefore, both ground pins can be connected directly together. it is recommended that these ground pins be connected at the ground for the input and output capacitors. ? if using the lfcsp package, the exposed pad must be soldered at the board to the gnd1 and/or gnd2 pin(s). ? unused diode pins (pin d1 to pin d7) can be connected to ground, vout, or remain floating. however, the unused diode current sinks must be disabled by setting them as independent sinks in register 0x05 and then disabling them in register 0x10. if they are not disabled, the charge pump efficiency may suffer. ? if the cmp_in phototransistor input is not used, it can be connected to ground or remain floating. ? if the interrupt pin (nint) is not used, connect it to ground or leave it floating. never connect it to a voltage supply, except through a 1 k series resistor.
ADP8860 rev. 0 | page 25 of 52 ? the ADP8860 has an integrated noise filter on the nrst pin. under normal conditions, it is not necessary to filter the reset line. however, if exposed to an unusually noisy signal, then it is beneficial to add a small rc filter or bypass capacitor on this pin. if the nrst pin is not used, it must be pulled well above the v ih(min) level (see table 1 ). do not allow the nrst pin to float. example circuits v 07967-028 d3 d1 e3 d2 e4 d3 d4 d4 c4 d5 b4 d6 b3 d7 c3 cmp_in v out optional photosensor photosensor als 0.1f 0.1f e1 vddio nrst c2 vddio sda e2 vddio scl d2 vddio nint a3 v in 1f a4 gnd1 d1 gnd2 b1 c2+ b2 c2? c2 1f a1 c1+ c1 c1? c1 1f v out 1f a2 ADP8860 figure 44. generic application schematic keypad light up to 10 leds (6ma each) 60ma max total current accessory lights or sub-display bl ph1 main photosensor ph2 optional photosensor 0 7967-029 d3 d1 dl1 e3 d2 dl2 e4 d3 dl3 d4 d4 dl4 c4 d5 dl5 b4 d6/ cmp_in2 dl6 b3 d7 c3 cmp_in e1 r1 r2 r3 r4 vddio c2 sda e2 scl d2 b1 c2+ b2 c2? a1 c1+ vout gnd2 c1 c1? ADP8860 vin gnd1 a3 a4 v in a2 d1 display backlight dl7 r5 dl8 r6 dl17 r15 2.8v nrst nint nrst nint 0.1f 0.1f c2 1f c1 1f 1f 1f i 2 c control signals figure 45. application schemati c with keypad light control
ADP8860 rev. 0 | page 26 of 52 i 2 c programming and digital control the ADP8860 provides full software programmability to facilitate its adoption in various product architectures. the default i 2 c address is 0101010x (x = 0 during write, x = 1 during read). therefore, the default write address is 0x54 and the read address is 0x55. note the following general behavior of registers: ? all registers are set to their default values during reset or after a uvlo event. ? all registers are read/write unless otherwise specified. ? unused bits are read as zero. the following tables provide register and bit descriptions. the reset value for all bits in the bit map tables is all 0s, except in table 9 (see table 9 for its unique reset value). wherever the acronym n/a appears in the tables, it means not applicable. 0 1 0 1 0 1 0 r/w 0 0 0 st sp 0 = write 1 = read chip address reg address data ack ack ack 07967-030 figure 46. i 2 c command sequence table 7. register set definitions address register name description 0x00 mfdvid manufacturer and device id 0x01 mdcr device mode and status 0x02 mdcr2 device mode and status register 2 0x03 intr_en interrupts enable 0x04 cfgr configuration register 0x05 blsen sink enable backlight or independent 0x06 bloff backlight off timeout 0x07 bldim backlight dim timeout 0x08 blfr backlight fade in and out rates 0x09 blmx1 backlight (brightness level 1daylight) maximum current 0x0a bldm1 backlight (brightness level 1daylight) dim current 0x0b blmx2 backlight (brightness level 2office) maximum current 0x0c bldm2 backlight (brightness level 2office) dim current 0x0d blmx3 backlight (brightness level 3dark) maximum current 0x0e bldm3 backlight (brightness level 3dark) dim current 0x0f iscfr independent sink current fade control register 0x10 iscc independent sink current control register 0x11 isct1 independent sink current timer register led[7:5] 0x12 isct2 independent sink current timer register led[4:1] 0x13 iscf independent sink current fade register 0x14 isc7 independent sink current led7 0x15 isc6 independent sink current led6 0x16 isc5 independent sink current led5 0x17 isc4 independent sink current led4 0x18 isc3 independent sink current led3 0x19 isc2 independent sink current led2 0x1a isc1 independent sink current led1 0x1b ccfg comparator configuration 0x1c ccfg2 second comparator configuration 0x1d l2_trp l2 comparator reference 0x1e l2_hys l2 hysteresis 0x1f l3_trp l3 comparator reference
ADP8860 rev. 0 | page 27 of 52 address register name description 0x20 l3_hys l3 hysteresis 0x21 ph1levl first phototransistor ambient light levellow byte register 0x22 ph1levh first phototransistor ambient light levelhigh byte register 0x23 ph2levl second phototransistor am bient light levellow byte register 0x24 ph2levh second phototransistor ambi ent light levelhigh byte register table 8. register map addr reg. name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 0x00 mfdvid manufacture id device id 0x01 mdcr reserved int_cfg nstby dim_en reserved sis_en cmp_autoen blen 0x02 mdcr2 reserved short_int tsd_int ovp_int cmp2_int cmp_int 0x03 intr_en reserved short_ien tsd_ien ovp_ien cmp2_ien cmp_ien 0x04 cfgr reserved sel_ab cmp2_sel blv law fovr 0x05 blsen reserved d7en d6en d5en d4en d3en d2en d1en 0x06 bloff reserved offt 0x07 bldim reserved dimt 0x08 blfr bl_fo bl_fi 0x09 blmx1 reserved bl1_mc 0x0a bldm1 reserved bl1_dc 0x0b blmx2 reserved bl2_mc 0x0c bldm2 reserved bl2_dc 0x0d blmx3 reserved bl3_mc 0x0e bldm3 reserved bl3_dc 0x0f iscfr reserved sc_law 0x10 iscc reserved sc7_en sc6_en sc5_en sc4_en sc3_en sc2_en sc1_en 0x11 isct1 scon sc7off sc6off sc5off 0x12 isct2 sc4off sc3off sc2off sc1off 0x13 iscf scfo scfi 0x14 isc7 scr scd7 0x15 isc6 reserved scd6 0x16 isc5 reserved scd5 0x17 isc4 reserved scd4 0x18 isc3 reserved scd3 0x19 isc2 reserved scd2 0x1a isc1 reserved scd1 0x1b ccfg filt force_rd l3_out l2_out l3_en l2_en 0x1c ccfg2 filt2 force_rd2 l3_out2 l2_out2 l3_en2 l2_en2 0x1d l2_trp l2_trp 0x1e l2_hys l2_hys 0x1f l3_trp l3_trp 0x20 l3_hys l3_hys 0x21 ph1levl ph1lev_low 0x22 ph1levh reserved ph1lev_high 0x23 ph2levl ph2lev_low 0x24 ph2levh reserved ph2lev_high
ADP8860 rev. 0 | page 28 of 52 manufacturer and device id (mfdvid)register 0x00 this is a read-only register. table 9. mfdvid manufactur er and device id bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 manufacture id device id 0 0 0 0 0 1 1 1 mode control register (mdcr)register 0x01 table 10. mdcr mode control bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved int_cfg nstby dim_en reserved sis_en cmp_autoen bl_en table 11. bit descriptions for the mdcr register bit name bit no. description n/a 7 reserved. int_cfg 6 interrupt configuration. 1 = processor interrupt deasserts for 50 s and reasserts with pending events. 0 = processor interrupt remains asserted if the host trie s to clear the interrupt while there is a pending event. nstby 5 1 = device is in active mode. 0 = device is in standby mode, only the i 2 c interface is enabled. dim_en 4 dim_en is set by the hardware after a dim timeout. the user may also force the backlight into dim mode by asserting this bit. dim mode can only be entered if bl_en is also enabled. 1 = backlight is operating at the dim current level (bl_en must also be asserted). 0 = backlight is not in dim mode. n/a 3 reserved. sis_en 2 synchronous independent sinks enable. 1 = enables all led current sinks designated as independent sinks. all of the isc enable bits must be cleared; if any of the sc_en bits in register 0x10 are set, this bit has no effect. 0 = disables all sinks designated as independent sinks. all of the isc enable bits must be cleared; if any of the sc_en bits are set in register 0x10, this bit has no effect. cmp_autoen 1 1 = backlight automatically responds to the co mparator outputs (l2_out and l3_out). l2_en and/or l3_en must be set for this to function. blv values in register 0x04 are overridden. 0 = backlight does not autorespond to comparator level changes. the user can manually select backlight operating levels using bit blv in register 0x04. bl_en 0 1 = backlight is enabled (nstby must also be asserted). 0 = backlight is disabled.
ADP8860 rev. 0 | page 29 of 52 mode control register 2 (mdcr2)register 0x02 table 12. mdcr2 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved short_int tsd_int ovp_int cmp2_int cmp_int table 13. bit descriptions for the mdcr2 register bit name bit no. description 1 n/a 7:5 reserved. short_int 4 short-circuit error. 1 = a short-circuit or overload condition on vout was detected. 0 = no short-circuit or overload condition has been detected. tsd_int 3 thermal shutdown. 1 = the device temperature has exceeded 150c (typical). 0 = no overtemperature condition has been detected. ovp_int 2 overvoltage interrupt. 1 = vout has exceeded v ovp . 0 = vout has not exceeded v ovp . cmp2_int 1 1 = indicates that the second als comparator (cmp_in2) has changed state. 0 = the second sensor comparator has not triggered. cmp_int 0 1 = indicates that the main als comparator (cmp_in) has changed state. 0 = the main sensor comparator has not triggered. 1 interrupt bits are cleared by writin g a 1 to the flag; writing a 0 or reading the flag has no effect. interrupt enable (int r_en)register 0x03 table 14. intr_en bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved short_ien tsd_ien ovp_ien cmp2_ien cmp_ien table 15. bit descriptions for the intr_en register bit name bit no. description n/a 7:5 reserved. short_ien 4 short-circuit interrupt is enabled. when the short_in t status bit is set after an er ror condition, an interrupt is raised to the host if the short_ien flag is enabled. 1 = the short-circuit interrupt is enabled. 0 = the short-circuit interrupt is disabled (the short_int flag continues to assert). tsd_ien 3 thermal shutdown interrupt is enabled. when the tsd_in t status bit is set after an er ror condition, an interrupt is raised to the host if the tsd_ien flag is enabled. 1 = the thermal shutdown interrupt is enabled. 0 = the thermal shutdown interrupt is disabled (the tsd_int flag continues to assert). ovp_ien 2 overvoltage interrupt enabled. when the ovp_int status bit is set after an er ror condition, an interrupt is raised to the host if the ovp_ien flag is enabled. 1 = the overvoltage interrupt is enabled. 0 = the overvoltage interrupt is disabled (the ovp_int flag continues to assert). cmp2_ien 1 when the cmp2_int status bit is set after an enabled co mparator trips, an interrupt is raised if the cmp2_ien flag i s enabled. 1 = the second phototransistor comparator interrupt is enabled. 0 = the second phototransistor comparator interrupt is disabled (the cmp2_int flag continues to assert).
ADP8860 rev. 0 | page 30 of 52 bit name bit no. description cmp_ien 0 when the cmp_int status bit is set after an enabled comp arator trips, an interrupt is raised if the cmp_ien flag is enabled. 1 = the main comparator interrupt is enabled. 0 = the main comparator interrupt is disabled (the cmp_int flag continues to assert). backlight register descriptions configuration register (cfgr)register 0x04 table 16. cfgr bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sel_ab cmp2_sel blv law fovr table 17. bit descriptions for the cfgr register bit name bit no. description n/a 7 reserved. sel_ab 6 1 = selects the second phototransistor (cmp_in2) to control the backlight. 0 = selects the main phototransistor (cmp_in) to control the backlight. cmp2_sel 5 1 = the second phototransistor is en abled; the current sink on d6 is disabled. 0 = the second phototransistor is disabled. blv 4:3 brightness level. this field indicates the brightness level at which the device is operating. the software may force th e backlight to operate at one of the three brightness leve ls. setting cmp_autoen high (register 0x01) sets these values automatically and overwrites any previously written values. 00 = level 1 (daylight). 01 = level 2 (office). 10 = level 3 (dark). 11 = off (backlight set to 0 ma). law 2:1 backlight transfer law. 00 = linear law dac, linear time steps. 01 = square law dac, linear time steps. 10 = square law dac, nonlinear time steps (cubic 10). 11 = square law dac, nonlinear time steps (cubic 11). fovr 0 backlight fade override. 1 = the backlight fade override is enabled. 0 = the backlight fade override is disabled. backlight sink enable (blsen)register 0x05 table 18. blsen bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved d7en d6en d5en d4en d3en d2en d1en table 19. bit descriptions for the blsen register bit name bit no. description n/a 7 reserved. d7en 6 diode 7 backlight sink enable. 1 = selects led7 as an independent sink. 0 = connects led7 sink to backlight enable (bl_en). d6en 5 diode 6 backlight sink enable. 1 = selects led6 as an independent sink. 0 = connects led6 sink to backlight enable (bl_en).
ADP8860 rev. 0 | page 31 of 52 bit name bit no. description d5en 4 diode 5 backlight sink enable. 1 = selects led5 as an independent sink. 0 = connects led5 sink to backlight enable (bl_en). d4en 3 diode 4 backlight sink enable. 1 = selects led4 as independent sink. 0 = connects led4 sink to backlight enable (bl_en). d3en 2 diode 3 backlight sink enable. 1 = selects led3 as independent sink. 0 = connects led3 sink to backlight enable (bl_en). d2en 1 diode 2 backlight sink enable. 1 = selects led2 as independent sink. 0 = connects led2 sink to backlight enable (bl_en). d1en 0 diode 1 backlight sink enable. 1 = selects led1 as independent sink. 0 = connects led1 sink to backlight enable (bl_en). backlight off timeout (bloff)register 0x06 table 20. bloff bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved offt table 21. bit descriptions for the bloff register bit name bit no. description n/a 7 reserved. offt 6:0 backlight off timeout. after the off timeout (offt) pe riod, the backlight turns off. if the dim timeout (dimt) is enabled, the off timeout starts after the dim timeout. 0000 = timeout disabled 0000001 = 1 sec 0000010 = 2 sec 0000011 = 3 sec 1111111 = 127 sec backlight dim timeout (bldim)register 0x07 table 22. bldim bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved dimt table 23. bit descriptions for the bldim register bit name bit no. description n/a 7 reserved. dimt 6:0 backlight dim timeout. after the dim timeout (dimt) period, the backlight is set to the dim current value. the dim timeout starts after backlight reaches the maximum current. 0000 = timeout disabled 0000001 = 1 sec 0000010 = 2 sec 0000011 = 3 sec 1111111 = 127 sec
ADP8860 rev. 0 | page 32 of 52 backlight fade (blfr)register 0x08 table 24. blfr backlight fade bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bl_fo bl_fi table 25. bit descriptions for the blfr register bit name bit no. description bl_fo 7:4 backlight fade out rate. if the fade out is disabl ed (bl_fo = 0000), the backlight changes instantly (within 100 ms). if the fade out rate is set, the backlight fades from its current value to the dim or the off value. the times listed for bl_fo are for a full-scale fade out (30 ma to 0 ma). fades betwee n closer current values reduce the fade time. see the automated fade in and fade out section for more information. 0000 = 0.1 sec (fade out disabled) 1 0001 = 0.3 sec 0010 = 0.6 sec 0011 = 0.9 sec 0100 = 1.2 sec 0101 = 1.5 sec 0110 = 1.8 sec 0111 = 2.1 sec 1000 = 2.4 sec 1001 = 2.7 sec 1010 = 3.0 sec 1011 = 3.5 sec 1100 = 4.0 sec 1101 = 4.5 sec 1110 = 5.0 sec 1111 = 5.5 sec bl_fi 3:0 backlight fade in rate. if the fade in is disabl ed (bl_fi = 0000), the backlight changes instantly (within 100 ms). if the fade in rate is set, the backlight fades from its current va lue to its maximum when the backlight is turned on. the times listed for bl_fi are for a full-scale fade in (0 ma to 30 ma). fades between closer current values reduce the fade time. see the automated fade in and fade out section for more information. 0000 = 0.1 sec (fade in disabled) 1 0001 = 0.3 sec 0010 = 0.6 sec 0011 = 0.9 sec 1111 = 5.5 sec 1 when fade in and fade out are disabled, the backlight does not instantaneously fade, but instead, fades rapidly within about 1 00 ms.
ADP8860 rev. 0 | page 33 of 52 backlight level 1 (daylight) maximum cu rrent register (blmx1)register 0x09 table 26. blmx1 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bl1_mc table 27. bit descriptions for the blmx1 register bit name bit no. description n/a 7 reserved. bl1_mc 6:0 backlight maximum level 1 (daylight) current. the backlight maximum current can be set according to the linear or square law function, as follows (see table 28 for a complete list of values): dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.708 0.017 1111111 30 30 table 28. linear and square law currents per dac code dac code linear law (ma) square law 1 (ma) 0x00 0 0.000 0x01 0.236 0.002 0x02 0.472 0.007 0x03 0.709 0.017 0x04 0.945 0.030 0x05 1.181 0.047 0x06 1.417 0.067 0x07 1.654 0.091 0x08 1.890 0.119 0x09 2.126 0.151 0x0a 2.362 0.186 0x0b 2.598 0.225 0x0c 2.835 0.268 0x0d 3.071 0.314 0x0e 3.307 0.365 0x0f 3.543 0.419 0x10 3.780 0.476 0x11 4.016 0.538 0x12 4.252 0.603 0x13 4.488 0.671 0x14 4.724 0.744 0x15 4.961 0.820 0x16 5.197 0.900 0x17 5.433 0.984 0x18 5.669 1.071 0x19 5.906 1.163 0x1a 6.142 1.257 0x1b 6.378 1.356 0x1c 6.614 1.458 0x1d 6.850 1.564 0x1e 7.087 1.674 dac code linear law (ma) square law 1 (ma) 0x1f 7.323 1.787 0x20 7.559 1.905 0x21 7.795 2.026 0x22 8.031 2.150 0x23 8.268 2.279 0x24 8.504 2.411 0x25 8.740 2.546 0x26 8.976 2.686 0x27 9.213 2.829 0x28 9.449 2.976 0x29 9.685 3.127 0x2a 9.921 3.281 0x2b 10.157 3.439 0x2c 10.394 3.601 0x2d 10.630 3.767 0x2e 10.866 3.936 0x2f 11.102 4.109 0x30 11.339 4.285 0x31 11.575 4.466 0x32 11.811 4.650 0x33 12.047 4.838 0x34 12.283 5.029 0x35 12.520 5.225 0x36 12.756 5.424 0x37 12.992 5.627 0x38 13.228 5.833 0x39 13.465 6.043 0x3a 13.701 6.257 0x3b 13.937 6.475 0x3c 14.173 6.696 0x3d 14.409 6.921
ADP8860 rev. 0 | page 34 of 52 dac co de linear law (ma) square law 1 (ma) 0x3e 14.646 7.150 0x3f 14.882 7.382 0x40 15.118 7.619 0x41 15.354 7.859 0x42 15.591 8.102 0x43 15.827 8.350 0x44 16.063 8.601 0x45 16.299 8.855 0x46 16.535 9.114 0x47 16.772 9.376 0x48 17.008 9.642 0x49 17.244 9.912 0x4a 17.480 10.185 0x4b 17.717 10.463 0x4c 17.953 10.743 0x4d 18.189 11.028 0x4e 18.425 11.316 0x4f 18.661 11.608 0x50 18.898 11.904 0x51 19.134 12.203 0x52 19.370 12.507 0x53 19.606 12.814 0x54 19.842 13.124 0x55 20.079 13.439 0x56 20.315 13.757 0x57 20.551 14.078 0x58 20.787 14.404 0x59 21.024 14.733 0x5a 21.260 15.066 0x5b 21.496 15.403 0x5c 21.732 15.743 0x5d 21.968 16.087 0x5e 22.205 16.435 dac code linear law (ma) square law 1 (ma) 0x5f 22.441 16.787 0x60 22.677 17.142 0x61 22.913 17.501 0x62 23.150 17.863 0x63 23.386 18.230 0x64 23.622 18.600 0x65 23.858 18.974 0x66 24.094 19.351 0x67 24.331 19.733 0x68 24.567 20.118 0x69 24.803 20.507 0x6a 25.039 20.899 0x6b 25.276 21.295 0x6c 25.512 21.695 0x6d 25.748 22.099 0x6e 25.984 22.506 0x6f 26.220 22.917 0x70 26.457 23.332 0x71 26.693 23.750 0x72 26.929 24.173 0x73 27.165 24.599 0x74 27.402 25.028 0x75 27.638 25.462 0x76 27.874 25.899 0x77 28.110 26.340 0x78 28.346 26.784 0x79 28.583 27.232 0x7a 28.819 27.684 0x7b 29.055 28.140 0x7c 29.291 28.599 0x7d 29.528 29.063 0x7e 29.764 29.529 0x7f 30.000 30.000 1 cubic 10 and cubic 11 laws use the square law dac setting but vary the time step per dac code (see ). figure 31
ADP8860 rev. 0 | page 35 of 52 backlight level 1 (daylight) dim curren t register (bldm1)register 0x0a table 29. bldm1 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bl1_dc table 30. bit descriptions for the bldm1 register bit name bit no. description n/a 7 reserved. bl1_dc 6:0 backlight level 1 (daylight) dim current. the backli ght is set to the dim current value after a dim timeout or if the dim_en flag is set by the user (see table 28 for a complete list of values). dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 1111111 30 30 backlight level 2 (office) maximum curr ent register (blmx2)register 0x0b table 31. blmx2 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bl2_mc table 32. bit descriptions for the blmx2 register bit name bit no. description n/a 7 reserved. bl2_mc 6:0 backlight level 2 (office) maximum current (see table 28 for a complete list of values). dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 1111111 30 30
ADP8860 rev. 0 | page 36 of 52 backlight level 2 (office) dim curren t register (bldm2)register 0x0c table 33. bldm2 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bl2_dc table 34. bit descriptions for the bldm2 register bit name bit no. description n/a 7 reserved. bl2_dc 6:0 backlight level 2 (office) dim current. see table 28 for a complete list of values. the backlight is set to the dim current value after a dim timeout or if the dim_en flag is set by the user. dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 1111111 30 30 backlight level 3 (dark) maximum current register (blmx3)register 0x0d table 35. blmx3 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bl3_mc table 36. bit descriptions for the blmx3 register bit name bit no. description n/a 7 reserved. bl3_mc 6:0 backlight level 3 (dark) maximum current. see table 28 for a complete list of values. dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 1111111 30 30
ADP8860 rev. 0 | page 37 of 52 backlight level 3 (dark) dim current register (bldm3)register 0x0e table 37. bldm3 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved bl3_dc table 38. bit descriptions for the bldm3 register bit name bit no. description n/a 7 reserved. bl3_dc 6:0 backlight level 3 (dark) dim current. see table 28 for a complete list of values. the backlight is set to the dim current value after a dim timeout or if the dim_en flag is set by the user. dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 1111111 30 30 independent sink register descriptions independent sink current fade control register (iscfr)register 0x0f table 39. iscfr bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sc_law table 40. bit descriptions for the iscfr bit name bit no. description n/a 7:2 reserved. sc_law 1:0 independent sink current fade transfer law. 00 = linear law dac, linear time steps. 01 = square law dac, linear time steps. 10 = square law dac, nonlinear time steps (cubic 10). 11 = square law dac, nonlinear time steps (cubic 11). independent sink current control (iscc)register 0x10 table 41. iscc bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved sc7_en sc6_en sc5_en sc4_en sc3_en sc2_en sc1_en table 42. bit descriptions for the iscc register bit name bit no. description n/a 7 reserved. sc7_en 6 this enable acts upon the led7. 1 = sc7 is turned on. 0 = sc7 is turned off. sc6_en 5 this enable acts upon the led6. 1 = sc6 is turned on. 0 = sc6 is turned off. sc5_en 4 this enable acts upon the led5. 1 = sc5 is turned on. 0 = sc5 is turned off.
ADP8860 rev. 0 | page 38 of 52 bit name bit no. description sc4_en 3 this enable acts upon the led4. 1 = sc4 is turned on. 0 = sc4 is turned off. sc3_en 2 this enable acts upon the led3. 1 = sc3 is turned on. 0 = sc3 is turned off. sc2_en 1 this enable acts upon the led2. 1 = sc2 is turned on. 0 = sc2 is turned off. sc1_en 0 this enable acts upon the led1. 1 = sc1 is turned on. 0 = sc1 is turned off. independent sink current time (isct1)register 0x11 table 43. isct1 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scon sc7off sc6off sc5off table 44. bit descriptions for the isct1 register bit name bit no. description 1 , 2 scon 7:6 sc on time. if the scxoff time is not disabled, then when the independent current sink is enabled (register 0x10) it remains on for the on time selected (per the following list) and then turns off. 00 = 0.2 sec. 01 = 0.6 sec. 10 = 0.8 sec. 11 = 1.2 sec. sc7off 5:4 sc7 off time. when the sc off time is disabled, the isc remains on while enabled. when the sc off time is set to any other value, the isc turns off for the off time (per the followi ng listed times) and then turns on according to the scon setting. 00 = off time disabled. 01 = 0.6 sec. 10 = 1.2 sec. 11 = 1.8 sec. sc6off 3:2 sc6 off time. when the sc off time is disabled, the isc remains on while enabled. when the sc off time is set to any other value, the isc turns off for the off time (per the followi ng listed times) and then turns on according to the scon setting. 00 = off time disabled. 01 = 0.6 sec. 10 = 1.2 sec. 11 = 1.8 sec. sc5off 1:0 sc5 off time. when the sc off time is disabled, the isc remains on while enabled. when the sc off time is set to any other value, the isc turns off for the off time (per the followi ng listed times) and then turns on according to the scon setting. 00 = off time disabled. 01 = 0.6 sec. 10 = 1.2 sec. 11 = 1.8 sec. 1 an independent sink remains on continuously wh en scx_en = 1 and scx_off is 00 (disabled). 2 to enable multiple independent sinks, set the appropriate scx_en bits. to create equivalent blinking and fading sequences, enab le all independent sinks in one write cycle to cause a preprogrammed se quence to start simultaneously.
ADP8860 rev. 0 | page 39 of 52 independent sink current time (isct2)register 0x12 table 45. isct2 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 sc4off sc3off sc2off sc1off table 46. bit descriptions for the isct2 register designation bit description 1 , 2 sc4off 7:6 sc4 off time. when the sc off time is disabled, the isc remains on while enabled. when the sc off time is set to any other value, then the isc turns off for the off time (per th e following listed times) and then turns on according to the scon setting. 00 = off time disabled. 01 = 0. 6 sec. 10 = 1.2 sec. 11 = 1.8 sec. sc3off 5:4 sc3 off time. when the sc off time is disabled, the isc remains on while enabled. when the sc off time is set to any other value, then the isc turns off for the off time (per th e following listed times) and then turns on according to the scon setting. 00 = off time disabled. 01 = 0. 6 sec. 10 = 1.2 sec. 11 = 1.8 sec. sc2off 3:2 sc2 off time. when the sc off time is disabled, the isc remains on while enabled. when the sc off time is set to any other value, then the isc turns off for the off time (per th e following listed times) and then turns on according to the scon setting. 00 = off time disabled. 01 = 0. 6 sec. 10 = 1.2 sec. 11 = 1.8 sec. sc1off 1:0 sc1 off time. when the sc off time is disabled, the isc remains on while enabled. when the sc off time is set to any other value, then the isc turns off for the off time (per th e following listed times) and then turns on according to the scon setting. 00 = off time disabled. 01 = 0. 6 sec. 10 = 1.2 sec. 11 = 1.8 sec. 1 an independent sink remains on continuously wh en scx_en = 1 and scx_off is 00 (disabled). 2 to enable multiple independent sinks, set the appropriate scx_en bits. to create equivalent blinking and fading sequences, enab le all independent sinks in one write cycle. this causes a preprogrammed sequence to start simultaneously.
ADP8860 rev. 0 | page 40 of 52 independent sink current fade (iscf)register 0x13 table 47. iscf bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scfo scfi table 48. bit descriptions for the iscf register bit name bit no. description scfo 7:4 sink current fade out rate. the following times listed are for a full-scale fade out (30 ma to 0 ma). fades between closer current values reduce the fade time. see the automated fade in and fade out section for more information. 0000 = disabled. 0001 = 0.30 sec. 0010 = 0.60 sec. 0011 = 0.90 sec. 0100 = 1.2 sec. 0101 = 1.5 sec. 0110 = 1.8 sec. 0111 = 2.1 sec. 1000 = 2.4 sec. 1001 = 2.7 sec. 1010 = 3.0 sec. 1011 = 3.5 sec. 1100 = 4.0 sec. 1101 = 4.5 sec. 1110 = 5.0 sec. 1111 = 5.5 sec. scfi 3:0 sink current fade in rate. the following times listed are for a full-scale fade in (0 ma to 30 ma). fades between clos er current values reduce the fade time. see the automated fade in and fade out section for more information. 0000 = disabled. 0001 = 0.30 sec. 0010 = 0.60 sec. 0011 = 0.90 sec. 0100 = 1.2 sec. 0101 = 1.5 sec. 0110 = 1.8 sec. 0111 = 2.1 sec. 1000 = 2.4 sec. 1001 = 2.7 sec. 1010 = 3.0 sec. 1011 = 3.5 sec. 1100 = 4.0 sec. 1101 = 4.5 sec. 1110 = 5.0 sec. 1111 = 5.5 sec.
ADP8860 rev. 0 | page 41 of 52 sink current register led7 (isc7)register 0x14 table 49. isc7 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 scr scd7 table 50. bit descriptions for the isc7 register bit name bit no. description scr 7 1 = sink current 1. 0 = sink current 0. for the lowest input current consum ption and optimal efficiency, set scr to 0 when d7 is set to isc in register 0x05 and sc7_en = 0. scd7 6:0 for sink current 0, use the following dac code schedule (see table 28 for a complete list of values): dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 1111111 30 30 for sink current 1, use the following dac code schedule (see table 51 for a complete list of values): dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.472 0.004 0000010 0.945 0.014 0000011 01.417 0.034 1111111 60 60 table 51. linear and square law currents for led7 (scr = 1) dac code linear law (ma) square law 1 (ma) 0x00 0.000 0 0x01 0.472 0.004 0x02 0.945 0.014 0x03 1.42 0.034 0x04 1.89 0.06 0x05 2.36 0.094 0x06 2.83 0.134 0x07 3.31 0.182 0x08 3.78 0.238 0x09 4.25 0.302 0x0a 4.72 0.372 0x0b 5.20 0.45 0x0c 5.67 0.536 0x0d 6.14 0.628 0x0e 6.61 0.73 0x0f 7.09 0.838 0x10 7.56 0.952 0x11 8.03 1.076 0x12 8.50 1.206 0x13 8.98 1.342 dac code linear law (ma) square law 1 (ma) 0x14 9.45 1.488 0x15 9.92 1.64 0x16 10.39 1.8 0x17 10.87 1.968 0x18 11.34 2.142 0x19 11.81 2.326 0x1a 12.28 2.514 0x1b 12.76 2.712 0x1c 13.23 2.916 0x1d 13.70 3.128 0x1e 14.17 3.348 0x1f 14.65 3.574 0x20 15.12 3.81 0x21 15.59 4.052 0x22 16.06 4.3 0x23 16.54 4.558 0x24 17.01 4.822 0x25 17.48 5.092 0x26 17.95 5.372 0x27 18.43 5.658
ADP8860 rev. 0 | page 42 of 52 dac code linear law (ma) square law 1 (ma) 0x28 18.90 5.952 0x29 19.37 6.254 0x2a 19.84 6.562 0x2b 20.31 6.878 0x2c 20.79 7.202 0x2d 21.26 7.534 0x2e 21.73 7.872 0x2f 22.20 8.218 0x30 22.68 8.57 0x31 23.15 8.932 0x32 23.62 9.3 0x33 24.09 9.676 0x34 24.57 10.058 0x35 25.04 10.45 0x36 25.51 10.848 0x37 25.98 11.254 0x38 26.46 11.666 0x39 26.93 12.086 0x3a 27.40 12.514 0x3b 27.87 12.95 0x3c 28.35 13.392 0x3d 28.82 13.842 0x3e 29.29 14.3 0x3f 29.76 14.764 0x40 30.24 15.238 0x41 30.71 15.718 0x42 31.18 16.204 0x43 31.65 16.7 0x44 32.13 17.202 0x45 32.60 17.71 0x46 33.07 18.228 0x47 33.54 18.752 0x48 34.02 19.284 0x49 34.49 19.824 0x4a 34.96 20.37 0x4b 35.43 20.926 0x4c 35.91 21.486 0x4d 36.38 22.056 0x4e 36.85 22.632 0x4f 37.32 23.216 0x50 37.80 23.808 0x51 38.27 24.406 0x52 38.74 25.014 0x53 39.21 25.628 dac code linear law (ma) square law 1 (ma) 0x54 39.69 26.248 0x55 40.16 26.878 0x56 40.63 27.514 0x57 41.10 28.156 0x58 41.57 28.808 0x59 42.05 29.466 0x5a 42.52 30.132 0x5b 42.99 30.806 0x5c 43.46 31.486 0x5d 43.94 32.174 0x5e 44.41 32.87 0x5f 44.88 33.574 0x60 45.35 34.284 0x61 45.83 35.002 0x62 46.30 35.726 0x63 46.77 36.46 0x64 47.24 37.2 0x65 47.72 37.948 0x66 48.19 38.702 0x67 48.66 39.466 0x68 49.13 40.236 0x69 49.61 41.014 0x6a 50.08 41.798 0x6b 50.55 42.59 0x6c 51.02 43.39 0x6d 51.50 44.198 0x6e 51.97 45.012 0x6f 52.44 45.834 0x70 52.91 46.664 0x71 53.39 47.5 0x72 53.86 48.346 0x73 54.33 49.198 0x74 54.80 50.056 0x75 55.28 50.924 0x76 55.75 51.798 0x77 56.22 52.68 0x78 56.69 53.568 0x79 57.17 54.464 0x7a 57.64 55.368 0x7b 58.11 56.28 0x7c 58.58 57.198 0x7d 59.06 58.126 0x7e 59.53 59.058 0x7f 60 60 1 cubic 10 and cubic 11 laws use the square law dac setting but vary the time step per dac code (see figure 31).
ADP8860 rev. 0 | page 43 of 52 sink current register led6 (isc6)register 0x15 table 52. isc6 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved scd6 table 53. bit descriptions for the isc6 register bit name bit no. description n/a 7 reserved. scd6 6:0 sink current. use the following dac code schedule (see table 28 for a complete list of values): dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 1111111 30 30 sink current register led5 (isc5)register 0x16 table 54. isc5 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved scd5 table 55. bit descriptions for the isc5 register bit name bit no. description n/a 7 reserved. scd5 6:0 sink current. use the following dac code schedule (see table 28 for a complete list of values): dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 1111111 30 30 sink current register led4 (isc4)register 0x17 table 56. isc4 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved scd4 table 57. bit descriptions for the isc4 register bit name bit no. description n/a 7 reserved. scd4 6:0 sink current. use the following dac code schedule (see table 28 for a complete list of values): dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 1111111 30 30
ADP8860 rev. 0 | page 44 of 52 sink current register led3 (isc3)register 0x18 table 58. isc3 b it map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved scd3 table 59. bit descriptions for the isc3 register bit name bit no. description n/a 7 reserved. scd3 6:0 sink current. use the following dac code schedule (see table 28 for a complete list of values): dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 1111111 30 30 sink current register led2 (isc2)register 0x19 table 60. isc2 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved scd2 table 61. bit descriptions for the isc2 register bit name bit no. description n/a 7 reserved. scd2 6:0 sink current. use the following dac code schedule (see table 28 for a complete list of values): dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 1111111 30 30 sink current register led1 (isc1)register 0x1a table 62. isc1 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved scd1 table 63. bit descriptions for the isc1 register bit name bit no. description n/a 7 reserved scd1 6:0 sink current. use the following dac code schedule (see table 28 for a complete list of values): dac linear law (ma) square law (ma) 0000000 0 0 0000001 0.236 0.002 0000010 0.472 0.007 0000011 0.709 0.017 1111111 30 30
ADP8860 rev. 0 | page 45 of 52 comparator register descriptions comparator configuration (ccfg)register 0x1b table 64. ccfg bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 filt force_rd l3_out l2_out l3_en l2_en table 65. bit descriptions for the ccfg register bit name bit no. description filt 7:5 filter setting for the cmp_in light sensor. 000 = 80 ms. 001 = 160 ms. 010 = 320 ms. 011 = 640 ms. 100 = 1280 ms. 101 = 2560 ms. 110 = 5120 ms. 111= 10,240 ms. force_rd 4 force a read of the cmp_in light sensor while inde pendent sinks are running, but the backlight is not. reset by chi p after the conversion is complete and l2_out and l3_o ut are valid. ignored if the backlight is enabled. l3_out 3 this bit is the o utput of the l3 comparator. l2_out 2 this bit is the o utput of the l2 comparator. l3_en 1 1 = the l3 comparator is enabled for the cmp_in comparator. 0 = the l3 comparator is disabled for the cmp_in comparator. l2_en 0 note that the l3 comparator has priority over l2. 1 = the l2 comparator is enabled for the cmp_in comparator. 0 = the l2 comparator is disabled for the cmp_in comparator. second comparator configuration (ccfg2)register 0x1c table 66. ccfg2 bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 filt2 force_rd2 l3_out2 l2_out2 l3_en2 l2_en2 table 67. bit descriptions for the ccfg2 register bit name bit no. description filt2 7:5 filter setting for the cmp_in2 light sensor. 000 = 80 ms. 001 = 160 ms. 010 = 320 ms. 011 = 640 ms. 100 = 1280 ms. 101 = 2560 ms. 110 = 5120 ms. 111= 10,240 ms. force_rd2 4 force a read of the cmp_in2 light sensor while in dependent sinks are running, but the backlight is not. reset by chip after the conversion is complete and l2_out and l3 _out are valid. ignored if the backlight is enabled. l3_out2 3 this bit is the output of the l3 comparator for the second light sensor. l2_out2 2 this bit is the output of the l2 comparator for the second light sensor. l3_en2 1 1 = the l3 comparator is enabled for the cmp_in2 comparator. 0 = the l3 comparator is disabled for the cmp_in2 comparator.
ADP8860 rev. 0 | page 46 of 52 bit name bit no. description l2_en2 0 note that the l3 comp arator has priority over l2. 1 = the l2 comparator is enabled for the cmp_in2 comparator. 0 = the l2 comparator is disabled for the cmp_in2 comparator. comparator level 2 threshol d (l2_trp)register 0x1d table 68. l2_trp bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l2_trp table 69. bit descriptions for the l2_trp register bit name bit no. description l2_trp 7:0 comparator level 2 threshold. if the comparat or input is below l2_trp, th en the comparator trips and the backlight enters level 2 (office) mode. the following lists the code settings for photosensor current: 00000000 = 0 a. 00000001 = 4.3 a. 00000010 = 8.6 a. 00000011 = 12.9 a. 1111 1010 = 1080 a. 11111111 = 1106 a. although codes above 1111010 (250) are possible, they should not be used. furthermore, the maximum value of l2_trp + l2_hys must not exceed 1111 010 (250). comparator level 2 hysteresis (l2_hys)register 0x1e table 70. l2_hys bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l2_hys table 71. bit descriptions for the l2_hys register bit name bit no. description l2_hys 7:0 comparator level 2 hysteresis. if the comparat or input is above l2_trp + l2_hys, the comparator trips and the backlight enters level 1 (daylight) mode. the following lists the code settings for photosensor current hysteresis: 0000000 = 0 a. 00000001 = 4.3 a. 00000010 = 8.6 a. 00000011 = 12.9 a. 1111 1010 = 1080 a. 11111111 = 1106 a. although codes above 1111010 (250) are possible, they should not be used. furthermore, the maximum value of l2_trp + l2_hys must not exceed 1111 010 (250).
ADP8860 rev. 0 | page 47 of 52 comparator level 3 threshol d (l3_trp)register 0x1f table 72. l3_trp bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l3_trp table 73. bit descriptions for the l3_trp register bit name bit no. description l3_trp 7:0 comparator level 3 threshold. if the comparat or input is below l3_trp, th e comparator trips and the backlight enters level 3 (dark) mode. the following lists the code settings for photosensor current: 0000000 = 0 a. 0000001 = 0.54 a. 0000010 = 1.08 a. 0000011 = 1.62 a. 1111111 = 137.7 a. comparator level 3 hyster esis (l3_hys)register 0x20 table 74. l3_hys comparator level 3 hysteresis bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 l3_hys table 75. bit descriptions for the l3_hys register bit name bit no. description l3_hys 7:0 comparator level 3 hysteresis. if the comparat or input is above l3_trp + l3_hys, the comparator trips and the backlight enters level 2 (office) mode. the following lists the code settings for photosensor current hysteresis: 0000000 = 0 a. 0000001 = 0.54 a. 0000010 = 1.08 a. 0000011 = 1.62 a. 1111111 = 137.7 a. first phototransistor register: low byte (ph1levl)register 0x21 table 76. ph1levl bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ph1lev_low table 77. bit descriptions for the ph1levl register bit name bit no. description ph1lev_low 7:0 13-bit conversion value for the first light sens orlow byte (bit 7 to bit 0). the value is updated every 80 ms (when the light sensor is enabled). this is a read-only register.
ADP8860 rev. 0 | page 48 of 52 first phototransistor register: high byte (ph1levh)register 0x22 table 78. ph1levh bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ph1lev_high table 79. bit descriptions for the ph1levh register bit name bit no. description n/a 7:5 reserved. ph1lev_high 4:0 13-bit conversion value for the first light sens orhigh byte (bit 12 to bit 8). the value is updated every 80 ms (when the light sensor is enabled). this is a read-only register. second phototransistor register: low byte (ph2levl)register 0x23 table 80. ph2levl bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 ph2lev_low table 81. bit descriptions for the ph2levl register bit name bit no. description ph2lev_low 7:0 13-bit conversion value for the second light sensorlow byte (bit 7 to bit 0) the value is updated every 80 ms (when the light sensor is enabled). this is a read-only register. second phototransistor register: high byte (ph2levh)register 0x24 table 82. ph2levh bit map bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 reserved ph2lev_high table 83. bit descriptions for the ph2levh register bit name bit no. description n/a 7:5 reserved. ph2lev_high 4:0 13-bit conversion value for the second light se nsorhigh byte (bit 12 to bit 8). the value is updated every 80 ms (when the light sensor is enabled). this is a read-only register.
ADP8860 rev. 0 | page 49 of 52 outline dimensions 0.645 0.600 0.555 1.995 1.955 1.915 a b c d e 1 2 3 4 bottom view (ball side up) top view (ball side down) 0.287 0.267 0.247 1.60 ref seating plane 0.40 ref 0.415 0.400 0.385 0.230 0.200 0.170 0.05 max coplanarity 2.395 2.355 2.315 ball a1 identifier 021009-a figure 47. 20-ball wafer level chip scale package [wlcsp] (cb-20-6) dimensions shown in millimeters 2.65 2.50 sq 2.35 3.75 bsc sq 4.00 bsc sq 1 0.50 bsc p i n 1 i n d i c a t o r 0.50 0.40 0.30 compliant to jedec standards mo-220-vggd-1 090408-b top view 12 max 0.80 max 0.65 typ seating plane pin 1 indi c ator coplanarity 0.08 1.00 0.85 0.80 0.30 0.23 0.18 0.05 max 0.02 nom 0.20 ref 20 6 16 10 11 15 5 exposed pad (bottom view) 0.60 max 0.60 max 0.25 min for proper connection of the exposed pad, refer to the pin configuration and function descriptions section of this data sheet. figure 48. 20-lead lead frame chip scale package [lfcsp_vq] 4 mm 4 mm body, very thin quad (cp-20-4) dimensions shown in millimeters
ADP8860 rev. 0 | page 50 of 52 ordering guide model temperature range package description package option ADP8860acbz-r7 1 ?40c to +85c 20-ball wlcsp, tape and reel cb-20-6 ADP8860acpz-r7 1 ?40c to +85c 20-lead lfcsp_vq, tape and reel cp-20-4 1 z = rohs compliant part. 07 967-033 07967-034 figure 49. tape and reel orientation for wlcsp units figure 50. tape and reel orientation for lfcsp units
ADP8860 rev. 0 | page 51 of 52 notes
ADP8860 rev. 0 | page 52 of 52 notes ?2009 analog devices, inc. all rights reserved. trademarks and registered trademarks are the prop erty of their respective owners. d07967-0-5/09(0)

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